1995 microchip technology inc. ds20067f-page 1 features single supply with programming operation down to 1.8v low power cmos technology - 70 m a typical active read current at 1.8v -2 m a typical standby current at 1.8v org pin selectable memory con?uration - 128 x 8 or 64 x 16 bit organization (93aa46) - 256 x 8 or 128 x 16 bit organization (93aa56) - 512 x 8 or 256 x 16 bit organization (93AA66) self-timed erase and write cycles (including auto-erase) automatic eral before wral power on/off data protection circuitry industry standard 3-wire serial i/o device status signal during erase/write cycles sequential read function 10,000,000 erase/write cycles guaranteed on 93aa56 and 93AA66 1,000,000 e/w cycles guaranteed on 93aa46* data retention > 200 years 8-pin pdip/soic (soic in jedec and eiaj standards) description the microchip technology inc. 93aa46/56/66 are 1k, 2k and 4k low voltage serial electrically erasable proms. the device memory is con?ured as x8 or x16 bits depending on the org pin setup. advanced cmos technology makes these devices ideal for low power non-volatile memory applications. the 93aa series is available in standard 8-pin dip and surface mount soic packages. the rotated pin-out 93aa46x/ 56x/66x are offered in the ?n?package only. package type block diagram 1
2
3
4 8
7
6
5 cs
clk
di
do ss v
nu
org
v cc 1
2
3
4 8
7
6
5 ss v
nu
org
v cc cs
clk
di
do 1
2
3
4 8
7
6
5 org
vss
do
di nu
vcc
cs
clk dip soic soic 93aa46 93aa56 93AA66 93aa46 93aa56 93AA66 93aa46x 93aa56x 93AA66x memory
array
address
decoder v cc v ss data register do mode
decode
logic clock
generator output
buffer di cs org clk address
counter 93aa46/56/66 1k/2k/4k 1.8v cmos serial eeprom *future: 10,000,000 cycles guaranteed
93aa46/56/66 ds20067f-page 2 1995 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ratings v cc ............................................................................ 7.0v all inputs and outputs w.r.t. v ss .......... -0.6v to v cc +1.0v storage temperature................................-65?c to +150?c ambient temp. with power applied...........-65?c to +125?c soldering temperature of leads (10 seconds)........+300?c esd protection on all pins ......................................... 4 kv *notice: stresses above those listed under ?aximum ratings may cause permanent damage to the device. this is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: pin function table name function cs chip select clk serial data clock di serial data input do serial data output v ss ground org memory con?uration nu not utilized v cc power supply table 1-2: dc and ac electrical characteristics v cc = +1.8v to +5.5v commercial (c): tamb = 0?c to +70?c parameter symbol min typ max units conditions high level input voltage v ih 1 2.0 v cc +1 v v cc 3 2.7v v ih 2 0.7 v cc ? cc +1 v v cc < 2.7v low level input voltage v il 1 -0.3 0.8 v v cc 3 2.7v v il 2 -0.3 0.2 v cc vv cc < 2.7v low level output voltage v ol 1 0.4 v i ol = 2.1 ma; v cc = 4.5v v ol 2 0.2 v i ol = 100 m a; v cc = 1.8v high level output voltage v oh 1 2.4 v i oh = -400 m a; v cc = 4.5v v oh 2v cc -0.2 v i oh = -100 m a; v cc = 1.8v input leakage current i li -10 10 m av in = 0.1v to v cc output leakage current i lo -10 10 m av out = 0.1v to v cc pin capacitance (all inputs/outputs) c in , c out 7 pfv in /v out = 0v (note 1 & 2) tamb = +25?c, f clk = 1 mhz operating current i cc write 3 ma f clk =2 mhz; v cc =5.5v (note 2) i cc read 70 1 500 ma m a m a f clk = 2 mhz; v cc = 5.5v f clk = 1 mhz; v cc = 3.0v f clk = 1 mhz; v cc = 1.8v standby current i ccs 2 100 30 m a m a m a clk = cs = 0v; v cc = 5.5v clk = cs = 0v; v cc = 3.0v clk = cs = 0v; v cc = 1.8v clock frequency f clk 2 mhz mhz v cc 3 4.5v v cc < 4.5v clock high time t ckh 250 1 ns clock low time t ckl 250 ns chip select setup time t css 50 ns relative to clk chip select hold time t csh 0 ns relative to clk chip select low time t csl 250 ns data input setup time t dis 100 ns relative to clk data input hold time t dih 100 ns relative to clk data output delay time t pd 400 ns cl = 100 pf data output disable time t cz 100 ns cl = 100 pf (note 2) status valid time t sv 500 ns cl = 100 pf program cycle time t wc 4 10 ms erase/write mode t ec 8 15 ms eral mode (vcc = 5v 10%) t wl 16 30 ms wral mode (vcc = 5v 10%) note 1: this parameter is tested at tamb = 25 c and f clk = 1 mhz. note 2: this parameter is periodically sampled and not 100% tested.
1995 microchip technology inc. ds20067f-page 3 93aa46/56/66 table 1-3: instruction set for 93aa46: org = 1 (x 16 organization) table 1-4: instruction set for 93aa46: org = 0 (x 8 organization) table 1-5: instruction set for 93aa56: org = 1 (x 16 organization) table 1-6: instruction set for 93aa56: org = 0 (x 8 organization) table 1-7: instruction set for 93AA66: org = 1 (x 16 organization) table 1-8: instruction set for 93AA66: org = 0 (x 8 organization) instruction sb opcode address data in data out req. clk cycles read 1 10 a5 a4 a3 a2 a1 a0 d15 - d0 25 ewen 1 00 1 1 x x x x high-z 9 erase 1 11 a5 a4 a3 a2 a1 a0 (rdy/bsy )9 eral 1 00 1 0 x x x x (rdy/bsy )9 write 1 01 a5 a4 a3 a2 a1 a0 d15 - d0 (rdy/bsy )25 wral 1 00 0 1 x x x x d15 - d0 (rdy/bsy )25 ewds 1 00 0 0 x x x x high-z 9 instruction sb opcode address data in data out req. clk cycles read 1 10 a6 a5 a4 a3 a2 a1 a0 d7 - d0 18 ewen 1 00 1 1 x x x x x high-z 10 erase 1 11 a6 a5 a4 a3 a2 a1 a0 (rdy/bsy )10 eral 1 00 1 0 x x x x x (rdy/bsy )10 write 1 01 a6 a5 a4 a3 a2 a1 a0 d7 - d0 (rdy/bsy )18 wral 1 00 0 1 x x x x x d7 - d0 (rdy/bsy )18 ewds 1 00 0 0 x x x x x high-z 10 instruction sb opcode address data in data out req. clk cycles read 1 10 x a6 a5 a4 a3 a2 a1 a0 d15 - d0 27 ewen 1 00 1 1 x x x x x x high-z 11 erase 1 11 x a6 a5 a4 a3 a2 a1 a0 (rdy/bsy )11 eral 1 00 1 0 x x x x x x (rdy/bsy )11 write 1 01 x a6 a5 a4 a3 a2 a1 a0 d15 - d0 (rdy/bsy )27 wral 1 00 0 1 x x x x x x d15 - d0 (rdy/bsy )27 ewds 1 00 0 0 x x x x x x high-z 11 instruction sb opcode address data in data out req. clk cycles read 1 10 x a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 20 ewen 1 00 1 1 x x x x x x x high-z 12 erase 1 11 x a7 a6 a5 a4 a3 a2 a1 a0 (rdy/bsy )12 eral 1 00 1 0 x x x x x x x (rdy/bsy )12 write 1 01 x a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 (rdy/bsy )20 wral 1 00 0 1 x x x x x x x d7 - d0 (rdy/bsy )20 ewds 1 00 0 0 x x x x x x x high-z 12 instruction sb opcode address data in data out req. clk cycles read 1 10 a7 a6 a5 a4 a3 a2 a1 a0 d15 - d0 27 ewen 1 00 1 1 x x x x x x high-z 11 erase 1 11 a7 a6 a5 a4 a3 a2 a1 a0 (rdy/bsy )11 eral 1 00 1 0 x x x x x x (rdy/bsy )11 write 1 01 a7 a6 a5 a4 a3 a2 a1 a0 d15 - d0 (rdy/bsy )27 wral 1 00 0 1 x x x x x x d15 - d0 (rdy/bsy) 27 ewds 1 00 0 0 x x x x x x high-z 11 instruction sb opcode address data in data out req. clk cycles read 1 10 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 20 ewen 1 00 1 1 x x x x x x x high-z 12 erase 1 11 a8 a7 a6 a5 a4 a3 a2 a1 a0 (rdy/bsy )12 eral 1 00 1 0 x x x x x x x (rdy/bsy )12 write 1 01 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 (rdy/bsy )20 wral 1 00 0 1 x x x x x x x d7 - d0 (rdy/bsy )20 ewds 1 00 0 0 x x x x x x x high-z 12
93aa46/56/66 ds20067f-page 4 1995 microchip technology inc. 2.0 functional description when the org pin is connected to v cc , the (x16) orga- nization is selected. when it is connected to ground, the (x8) organization is selected. instructions, addresses and write data are clocked into the di pin on the rising edge of the clock (clk). the do pin is nor- mally held in a high-z state except when reading data from the device, or when checking the ready/busy status during a programming operation. the ready/ busy status can be veri?d during an erase/write oper- ation by polling the do pin; do low indicates that pro- gramming is still in progress, while do high indicates the device is ready. the do will enter the high-z state on the falling edge of the cs. 2.1 st art condition the start bit is detected by the device if cs and di are both high with respect to the positive edge of clk for the ?st time. before a start condition is detected, cs, clk, and di may change in any combination (except to that of a start condition), without resulting in any device oper- ation (read, write, erase, ewen, ewds, eral, and wral). as soon as cs is high, the device is no longer in the standby mode. an instruction following a start condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. after execution of an instruction (i.e., clock in or out of the last required address or data bit) clk and di become don't care bits until a new start condition is detected. 2.2 di/do it is possible to connect the data in and data out pins together. however, with this con?uration it is possible for a ?us con?ct?to occur during the ?ummy zero that precedes the read operation, if a0 is a logic high level. under such a condition the voltage level seen at data out is unde?ed and will depend upon the relative impedances of data out and the signal source driving a0. the higher the current sourcing capability of a0, the higher the voltage at the data out pin. 2.3 data protection during power-up, all programming modes of operation are inhibited until v cc has reached a level greater than 1.4v. during power-down, the source data protection circuitry acts to inhibit all programming modes when v cc has fallen below 1.4v at nominal conditions. the ewen and ewds commands give additional pro- tection against accidentally programming during nor- mal operation. after power-up, the device is automatically in the ewds mode. therefore, an ewen instruction must be performed before any erase or write instruction can be executed. 3.0 read the read instruction outputs the serial data of the addressed memory location on the do pin. a dummy zero bit precedes the 16 bit (x16 organization) or 8 bit (x8 organization) output string. the output data bits will toggle on the rising edge of the clk and are stable after the speci?d time delay (t pd ). sequential read is possible when cs is held high. the memory data will automatically cycle to the next register and output sequentially. 4.0 erase/write enable and disable the 93aa46/56/66 power up in the erase/write dis- able (ewds) state. all programming modes must be preceded by an erase/write enable (ewen) instruc- tion. once the ewen instruction is executed, pro- gramming remains enabled until an ewds instruction is executed or v cc is removed from the device. to pro- tect against accidental data disturb, the ewds instruc- tion can be used to disable all erase/write functions and should follow all programming operations. execu- tion of a read instruction is independent of both the ewen and ewds instructions. 5.0 erase the erase instruction forces all data bits of the spec- i?d address to the logical "1" state. cs is brought low following the loading of the last address bit. this falling edge of the cs pin initiates the self-timed programming cycle. the do pin indicates the ready/busy status of the device if cs is brought high after a minimum of 250 ns low (t csl ). do at logical "0" indicates that program- ming is still in progress. do at logical "1" indicates that the register at the speci?d address has been erased and the device is ready for another instruction. the erase cycle takes 4 ms per word typical. 6.0 write the write instruction is followed by 16 bits (or by 8 bits) of data which are written into the speci?d address. after the last data bit is put on the di pin, cs must be brought low before the next rising edge of the clk clock. this falling edge of cs initiates the self- timed auto-erase and programming cycle. the do pin indicates the ready/busy status of the device if cs is brought high after a minimum of 250 ns low (t csl ) and before the entire write cycle is com- plete. do at logical "0" indicates that programming is still in progress. do at logical "1" indicates that the reg- ister at the speci?d address has been written with the data speci?d and the device is ready for another instruction. the write cycle takes 4 ms per word typical.
1995 microchip technology inc. ds20067f-page 5 93aa46/56/66 7.0 erase all the eral instruction will erase the entire memory array to the logical "1" state. the eral cycle is identi- cal to the erase cycle except for the different opcode. the eral cycle is completely self-timed and com- mences at the falling edge of the cs. clocking of the clk pin is not necessary after the device has entered the self clocking mode. the eral instruction is guar- anteed at 5v 10%. the do pin indicates the ready/busy status of the device if cs is brought high after a minimum of 250 ns low (t csl ) and before the entire write cycle is com- plete. the eral cycle takes (8 ms typical). 8.0 write all the wral instruction will write the entire memory array with the data speci?d in the command. the wral cycle is completely self-timed and commences at the falling edge of the cs. clocking of the clk pin is not necessary after the device has entered the self clocking mode. the wral command does include an automatic eral cycle for the device. therefore, the wral instruction does not require an eral instruction but the chip must be in the ewen status. the wral instruction is guaranteed at 5v 10%. the do pin indicates the ready/busy status of the device if cs is brought high after a minimum of 250 ns low (t csl ). the wral cycle takes 16 ms typical. 9.0 pin description 9.1 chip select (cs) a high level selects the device. a low level dese- lects the device and forces it into standby mode. how- ever, a programming cycle which is already initiated and/or in progress will be completed, regardless of the cs input signal. if cs is brought low during a pro- gram cycle, the device will go into standby mode as soon as the programming cycle is completed. cs must be low for 250 ns minimum (t csl ) between consecutive instructions. if cs is low, the internal control logic is held in a reset status. 9.2 serial clock (clk) the serial clock is used to synchronize the communi- cation between a master device and the 93aaxx. opcode, address, and data bits are clocked in on the positive edge of clk. data bits are also clocked out on the positive edge of clk. clk can be stopped anywhere in the transmission sequence (at high or low level) and can be contin- ued anytime with respect to clock high time (t ckh ) and clock low time (t ckl ). this gives the controlling master freedom in preparing opcode, address, and data. clk is a ?on't care?if cs is low (device deselected). if cs is high, but start condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for start condition). clk cycles are not required during the self-timed write (i.e., auto erase/write) cycle. after detection of a start condition the speci?d number of clock cycles (respectively low to high transitions of clk) must be provided. these clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (see instruc- tion set truth table). clk and di then become don't care inputs waiting for a new start condition to be detected. 9.3 data in (di) data in is used to clock in a start bit, opcode, address, and data synchronously with the clk input. 9.4 data out (do) data out is used in the read mode to output data syn- chronously with the clk input (t pd after the positive edge of clk). this pin also provides ready/busy status informa- tion during erase and write cycles. ready/busy status information is available on the do pin if cs is brought high after being low for minimum chip select low time (t csl ) and an erase or write operation has been initiated. the status signal is not available on do, if cs is held low or high during the entire write or erase cycle. in all other cases do is in the high-z mode. if status is checked after the write/erase cycle, a pull-up resistor on do is required to read the ready signal. 9.5 organization (org) when org is connected to v cc , the (x16) memory organization is selected. when org is tied to v ss , the (x8) memory organization is selected. org can only be ?ated for clock speeds of 1mhz or less for the (x16) memory organization. for clock speeds greater than 1 mhz, org must be tied to v cc or v ss . note: cs must go low between consecutive instructions.
93aa46/56/66 ds20067f-page 6 1995 microchip technology inc. figure 9-1: synchronous data timing figure 9-2: read timing figure 9-3: ewen timing clk status valid v ih v il cs t css t dis t dih t sv t csh t ckh t ckl t pd t cz t cz t pd v ih v il di v ih v il do (read) v oh v ol do (program) v oh v ol tri-state is a trademark of national semiconductor. clk cs t csl ?a ? a0 0 1 1 di do dx ?? d0 0 dx* ?? d0 dx* tri-state n d0 ?? clk cs t csl 0 0 1 di 1 1 ?? xx
1995 microchip technology inc. ds20067f-page 7 93aa46/56/66 figure 9-4: ewds timing figure 9-5: write timing figure 9-6: wral timing clk cs t csl 0 0 1 di 0 0 ?? xx clk cs tcsl 0 1 di ?? busy d0 ? 1 a0 ?? dx ready twc do tri-state n clk cs tcsl 0 1 di ?? busy d0 x 0 x ?? dx ready twl do 01 tri-state
93aa46/56/66 ds20067f-page 8 1995 microchip technology inc. figure 9-7: erase timing figure 9-8: eral timing clk cs tcsl 1 di an busy a0 ?? ready twc do 11 check status standby tcz tri-state tsv tri-state an-1 an-2 clk cs tcsl 1 di an busy a0 ?? ready twc do 11 check status standby tcz tri-state tsv tri-state an-1 an-2 ?guaranteed at v cc = 5.0v 10%.
1995 microchip technology inc. ds20067f-page 9 93aa46/56/66 notes
93aa46/56/66 ds20067f-page 10 1995 microchip technology inc. 93aa46/56/66 product identi cation system to order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales of?es. package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead sm = plastic soic (207 mil body), 8-lead (93aa46/56/66) temperature blank = 0 c to +70 c range: device: (x16) or (x8) con?uration 93aa46/56/66 cmos serial eeprom 93aa46/56/66x cmos serial eeprom in alternate pinouts (sn package only) 93aa46t/56t/66t cmos serial eeprom (tape and reel) 93aa46xt/56xt/66xt cmos serial eeprom (tape and reel) 93aa46/56/66 - /p americas (continued) san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408 436-7950 fax: 408 436-7955 asia/pacific hong kong microchip technology unit no. 3002-3004, tower 1 metroplaza 223 hing fong road kwai fong, n.t. hong kong tel: 852 2 401 1200 fax: 852 2 401 3431 korea microchip technology 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku, seoul, korea tel: 82 2 554 7200 fax: 82 2 558 5934 singapore microchip technology 200 middle road #10-03 prime centre singapore 188980 tel: 65 334 8870 fax: 65 334 8850 taiwan microchip technology 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2 717 7175 fax: 886 2 545 0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44 0 1628 851077 fax: 44 0 1628 850259 france arizona microchip technology sarl 2 rue du buisson aux fraises 91300 massy - france tel: 33 1 69 53 63 20 fax: 33 1 69 30 90 79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 muenchen, germany tel: 49 89 627 144 0 fax: 49 89 627 144 44 italy arizona microchip technology srl centro direzionale colleoni palazzo pegaso ingresso no. 2 via paracelso 23, 20041 agrate brianza (mi) italy tel: 39 039 689 9939 fax: 39 039 689 9883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81 45 471 6166 fax: 81 45 471 6122 9/5/95 americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602 786-7200 fax: 602 786-7277 technical support: 602 786-7627 web: http://www.mchip.com/biz/mchip atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770 640-0034 fax: 770 640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508 480-9990 fax: 508 480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 708 285-0071 fax: 708 285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 214 991-7177 fax: 214 991-8588 dayton microchip technology inc. 35 rockridge road englewood, oh 45322 tel: 513 832-2543 fax: 513 832-2841 los angeles microchip technology inc. 18201 von karman, suite 455 irvine, ca 92715 tel: 714 263-1888 fax: 714 263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516 273-5305 fax: 516 273-5335 "information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents arising from such use or otherwise. use of microchip's products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights." the microchip logo and name are registered trademarks of microchip technology inc. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. printed in the usa, 9/95 1995, microchip technology incorporated
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